手机 频道

手机CPU分析之后章 SC32442拼比PXA272


Samsung SC3 2442架构图


Samsung SC3 2442相关原理图


  三星SC3 2442处理器是一颗完全由三星电子研发的芯片,它包括AP(应用处理器)的内存板(多芯片封装),是一种适用于智能手机掌上电脑以及其他移动手持设置的解决方案。并具有低成本、低功耗以及高性能的优势。

  三星SC3 2442处理器的特点是采用ARM920T为核心,拥有一个16/32-bitRISC的微处理器,能提供应用于智能手机与手持装置的低功耗和高性能的微控制器解决方案,并开发利用了0.13umCMOS标准电池和存储编译器,大大减少了耗电量,且通过一套完整的通用系统节省了整体系统成本。

  三星SC3 2442还包括以下特性:独立的16kb指令缓存和16kb的数据高速缓存、MMU虚拟内存管理部件、晶体管和STNLCD控制器、基于NANDFLASH引导、系统经理(芯片选择逻辑和SDRAM控制器)、38192UART的、48192DMA、触摸屏接口、相机接口的IIC总线接口、USB设备、多媒体卡接口等等。

  Samsung SC3 2442特性:

  ARM920T的CPU核心 :
  64-way set-associative cache with :
   I-Cache (16 KB) and D-Cache (16 KB)
  Write-through and Write-back cache
  operation.
  MMU supports WinCE and LINUX.
   Internal AMBA bus architecture (AMBA2.0,AHB/APB)

  内存配置:
  MCP1 : 256Mb mSDRAM (x32) + 512Mb NAND (x8)
  MCP2 : 256Mb mSDRAM (x32) + 1Gb NAND (x8)
  MCP3 : 512Mb mSDRAM (x32) + 1Gb NAND (x8)
  MCP4 : 512Mb mSDRAM (x32) + 2Gb NAND (x8)
  MCP5 : 512Mb mSDRAM (x32)

  系统配备:
  Little/Big-Endian support
  Address space : 128MB for each bank (total 1GB)
  8 memory banks :
   - 6 memory banks for ROM, SRAM, and others
   - 2 memory banks for ROM/SRAM/SDRAM
  NAND Flash Boot Loader
   - 4 KB internal buffer for booting
   - Supports storage memory after booting
  Power Manager : supports STOP/SLEEP
  /IDLE mode

  运行环境:
  Internal : 1.35/1.5V
  External I/O : 2.3~3.6V
  Speed : 300MHz @1.35V
       400MHz @1.5V
  Memory : 1.8V

  外设支持:
  NAND Flash Controller (Normal/Advanced)
  LCD Controller (up to 4K color STN and 256K color TFT)
  with 1-ch LCD dedicated to DMA
  Camera Interface supporting up to 4096 x 4096
  resolution (2048 x 2048 pixel input support for
  scaling)
  USB Host/Device Interface
   - 2 ports USB Host (Version 1.1 Compliant)
   - 1 port USB Device (Version 1.1 Compliant)
  4-ch DMA Controllers
  3-ch UARTs with IrDA 1.0 (Including 64 byte FIFO)
  1-ch multi-master I2C-Bus Interface
  1-ch I2S-Bus Interface
  4-ch 16 bit PWMs (Pulse Width Modulation)
  and 1-ch 16-bit timer for OS
  130 multiplexed GPIO ports
  8-ch 10-bit ADCs (Max. 500KSPS), including
  TSP Controller
  16-bit Watch-dog Timer
  RTC with calendar function
  On-chip clock generator with PLL
  2-ch SPIs (Synchronous Serial I/O)
  SD Host/MMC (Multimedia Card) Interface
  Debug and TEST

  332 FBGA 14 X 14

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